1. Field of the Invention
This invention relates to methods and apparatus for correcting DC offset voltage in electronic circuits. More particularly, this invention relates to correction of DC offset compensation device automatically eliminating a DC offset voltage at the output of gain stage of a complex filter.
2. Description of Related Art
As is known in the art, the gain stages of a complex filter are operational amplifiers. It is further known in the art and explained in Design of Analog Integrated Circuits and Systems, Laker and Sansen, McGraw-Hill, New York, N.Y., January 1994, pp.: 448-450, “in an ideal op amp, if the input signal is zero, the output will also be zero. In an op amp, imperfections in the circuit components cause a DC voltage Vout to exist at the output, even when the input voltage is zero”. “The response at DC is not always critical, but excessive DC offset will alter the output waveform symmetry about zero volts; possibly causing the waveform to clip over a smaller range of signal amplitudes than would occur if the DC offset were absent. In other words, positive (or negative) DC offset may cause clipping to occur for positive (or negative) signal swings at a lower amplitude than for negative (or positive) swings. Consequently, the dynamic range for the op amp is reduced. This is particularly a problem in high gain situations”. In such situations, “a few millivolts of DC offset is amplified, with the signal, into the I V range. Applications like analog-to-digital converters require the DC voltages that represent digital codes to be determined very accurately. In these applications, internal offsets must be reduced to insignificance by offset nulling or auto-zero circuitry”.
Generally, in complex filter design, as shown in FIG. 1, the DC offset of an output node of a filter 5 is sensed by a DC offset sensing circuit 10 to determine the voltage level of the DC offset of the filter circuit 5. A compensation or corrective voltage is generated by the DC offset sensing circuit 10 and applied to a low pass filter 15. The low pass filter has a very low cut off frequency such that it output voltage is essentially a slowly varying DC voltage. The output of the low pass filter 15 is applied to the summing circuit 20 to be combined with the input signal vi 25 as the input to the filter 5. The compensation voltage when multiplied by the gain of the filter 5 has a magnitude equal to and a polarity opposite the voltage level of the DC offset of the filter circuit 10.
“A 1.4V, 13.5 mw, 10/100 mhz 6th Order Elliptic Filter/VGA with DC-Offset Correction in 90 nm CMOS”, Elmala, et al., Digest of Papers 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2005, pp.: 189-192, describes a highly linear variable gain amplifier (VGA) and filter operating at a low voltage with a DC-offset correction circuit. The DC-offset correction circuit rejects very low frequencies and requires very large resistances. The very large resistances are accomplished by operating transistors in a sub-threshold region.
“A Highly Linear Filter and VGA Chain with Novel DC-Offset Correction in 90 nm Digital CMOS Process”, Elmala, et al., Digest of Technical Papers—2005 Symposium on VLSI Circuits, June 2005, pp.: 302-303 presents a base-band filter that consists of a 6th order elliptic filter and five VGA stages. The filter is DC-offset free and has two options for DC offset cancellation, based on rejecting very low frequencies using sub-threshold devices to emulate very large resistor The first option uses an inter-stage high pass filter with 0.3 KHz cutoff frequency, in the feed forward path. The second option uses a low pass filter with 0.3 KHz cutoff in the feedback path to detect the DC information and generate a correction current to the input of the VGA chain.
“A Novel Offset Compensation Biquad Switched-Capacitor Filter Design” Qiang et al, Proceedings—5th International Conference on ASIC, October 2003, Vol. 1, pp.: 643-646 describes a biquad SC filter used in an RFID reader. The filter compensates the DC offset comes from the input and the internal offset originated by the mismatch within the differential circuit of the filter. And the output offset of our design is determined by the input offset of the integrator in the feedback path.
U.S. Pat. Nos. 6,937,083 and 6,806,756 (Manlove, et al.) describe an analog signal conditioning circuit for processing an analog signal generated by a sensor to remove DC offset. The signal conditioning circuit includes an amplifier that has an input receiving an analog input signal and an input receiving a reference signal. The amplifier includes an output providing an analog output signal defined by an amplified representation of the analog input signal and the reference signal. The circuitry includes a feedback circuit that has an input coupled to the amplifier output and an output coupled to the input of the amplifier for providing an analog feedback signal. The feedback circuit includes an analog-to-digital converter for converting the analog amplifier output to a digital signal, a digital controller for processing the digital signal, and a digital to analog converter for converting the processed digital signal to an analog feedback signal.
U.S. Pat. No. 6,909,882 (Hayashi, et al.) provides a signal processing semiconductor integrated circuit that includes a dummy low noise amplifier is used for the DC offset calibrations on the subsequent stage amplifiers. The calibrations are carried out during shifting into the reception mode in a state that a signal low noise amplifier is deactivated and the dummy low noise amplifier is activated to suppress generation of the DC offsets resulting from the leakage noises of the local oscillator during shifting into the reception mode, and to enhance the reception sensitivity.
U.S. Pat. No. 6,690,225 (Kondo, et al.) provides a DC offset canceling circuit for cancellation of DC offset regardless in TDMA systems and non-TDMA systems. One output signal having at least two or more phases is an input to a phase converter unit. A signal is an output from the phase converter unit is compared within a comparator unit to any one of other signals not applied to the phase converter unit. A comparison result is fed back to a signal processing section and DC offset components are cancelled.
U.S. Pat. No. 6,756,924 (Lee, et al.) teaches a signal processing apparatus for correcting DC offset in a communication system. The signal processing apparatus includes a low noise amplifier (LNA). A mixer combines the output from the low noise amplifier with a local oscillation signal. A first offset correction amplifier amplifies an output signal from the mixer eliminates DC offset in the output signal based on a first control signal. A second offset correction amplifier amplifies an output signal from the first offset correction amplifier and eliminates DC offset in the output signal based on a second control signal. A variable gain amplifier amplifies the output from the second offset correction amplifier. The gain of the variable gain amplifier is controlled such that power level of output be maintained to a desired value. An offset calibration device calibrates the DC offset in output of the variable gain amplifier. An offset correction device proved the first and second control signals derived from the output from the offset calibration device to eliminate DC offset in the output from the variable gain amplifier.
U.S. Pat. No. 6,642,767 (Wang) provides an apparatus for DC offset canceling. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.
U.S. Pat. No. 6,327,313 (Traylor, et al.) describes a method and apparatus for DC offset correction. The apparatus has a DC offset correction loop that utilizes a peak estimator to determine peaks associated with a digital signal. The peak estimator averages the peaks in order to estimate the DC offset. A summer sums the DC offset with the digital signal to produce a corrected output.
U.S. Pat. No. 6,114,980 (Tilley, et al.) illustrates a method and apparatus for settling a DC offset. The apparatus has a DC offset correction loop that utilizes a sign bit generator, a binary search stage, and a digital-to-analog converter in its feedback path to correct for DC offsets at the input of a gain stage.
U.S. Pat. No. 5,898,912 (Heck, et al.) teaches a direct current (DC) offset compensation method and apparatus within a receiver. The receiver includes input, output, forward path with filter, and feedback path with error amplifier coupled into the forward path. Coupled to the feedback path is an error signal storage device. A control circuit responds to input signal amplitude and is coupled to the storage device to retrieve stored error signal information for use by the feedback path. During calibration, a forward path stage is stimulated with a plurality of signals of known amplitude to generate outputs. The outputs are compared to a reference to generate error signals. The error signal values are stored in memory as a function of input signal amplitude. During operation, stage input signals are detected and compared with the signals of known amplitude. Upon detection of a match, the error signal value associated with the signal of interest is retrieved from memory and employed during DC offset compensation.
U.S. Pat. No. 5,760,629 (Urabe, et al.) describes a DC offset compensation device. The device has a level detector that detects variation of the amplitude of an input signal to output a level signal. A time constant control signal generates a time constant control signal based on the level signal to control a time constant of an estimator so as to make the time constant small for a prescribed period from a time when the level signal varies from HIGH to LOW. The estimator estimates DC offset included in the input signal with the time constant variation according to the time constant control signal to output an estimate. A compensator subtracts the estimate from the input signal to obtain a compensation output. Therefore, in the estimator, the speed of estimating the DC offset is different between a period corresponding to the head portion of the input signal and other periods. Thus, a DC offset compensation device can be configured to be capable of fast DC offset compensation at the head portion of the input signal and have stable DC offset compensation at the other portions.